基于VHDL语言的倒计时抢答器设计

Design of Countdown Responder Based on VHDL

分析了具有倒计时功能数字式抢答器的设计需求,给出了采用CPLD(复杂可编程逻辑器件)的系统设计方案,详细介绍了用VHDL(超高速集成电路硬件描述语言)进行其核心设计CPLD内部功能模块的具体设计及实现方法。总结了采用CPLD基于VHDL语言的系统设计优点,指出了现代数字系统设计的特点及发展趋势。

In this paper the design requirements of digital responder with countdown function is analyzed and a design concept of system with CPLD is presented. The design method of internal function module whose core design is based on VHDL is also introduced. This paper summarizes the advantages of system design with CPLD based on VHDL and points out the features and development trend of modern digital system.