基于FPGA的高斯白噪声发生器设计

Design of White Gaussian Noise Generator Based on FPGA

高斯白噪声发生器用于雷达系统和通信信道的测试,采用现场可编程门阵列(FPGA)实现噪声发生器的设计,在Altera公司的QuartusⅡ软件环境下,进行模块化设计方案,将FPGA实现的功能分为m序列产生模块、FIR数字滤波器模块、DDS模块和合成模块四个主要功能性模块,详细分析了m序列发生算法、FIR滤波算法和DDS算法。应用VHDL语言实现模块功能性设计。该系统采用CycloneⅡ芯片EP2C8N,输出噪声带宽可调,计算量小,可重复性好。

The white Gaussian noise generator is used to test the radar system and the communication channel. The noise generator is designed by FPGA technology. With the help of Quartus Ⅱ software of Altera Company, the function of FPGA is divided into four units,including m sequence generating unit,FIR filtering unit,DDS unit and synthesizing unit. The language VHDL is adopted to accomplish the unit design. The design uses the chip CycloneⅡ EP2C8N,and the output noise bandwidth can be adjusted, the computation is less, and the noise can be generated repeatedly.