基于VHDL语言的按键消抖电路设计及仿真

Design and Simulation of Key-jitter Eliminiation Circuit Based on VHDL

为了解决FPGA/CPLD系统的按键抖动问题,用VHDL语言有限状态机的方法,在S0状态下检测到有按键操作则转入延时状态S1,延时结束后,用状态S2,S3,S4对按键进行连续三次取样,如果三次取样均为低电平,则转入状态S5,并输出按键确认信号,否则,返回状态S0。电路经仿真分析,并下载到EPM7128ATC100芯片进行了验证,能够确保每次按键操作,产生一次按键确认,有很好的按键消抖效果,性能稳定。主要创新点是用VHDL语言有限状态机设计按键的消抖。

In order to solve key jitter of FPGA/CPLD system, using the method of VHDL finite state machine. In So mode, key operation is detected which is transferred to time delay mode S1. When the time delay has been finished,the continual three samples to the pressed key with condition S2 ,S3 ,S4 ,if three samples are the low levels,it changes to condition S5 ,and outputs the confirmation signal,waiting for the key release,otherwise,returns condition S0. By simulation and analysis,it is verified by the EMP7128ATC100. The effect is very good, and stable property. The main innovation is using finite state machine VHDL to realize key - jitter.