锁相环中数字分频器对输出信号相位噪声和杂散的影响

Effect of Digital Frequency Dividers on Spurs and PM Noise in PLL

基于对数字分频器混叠效应的分析,解释了锁相环相位噪声线形模型与一些实验结果误差较大的原因。并通过对数字分频器的建模,得到了数字分频器输出信号相位噪声和杂散的计算方法。实验证明这种方法的计算结果与实验结果相吻合。再以此修正锁相环相位噪声线形模型,使锁相环输出信号的相位噪声和杂散的预测能够更加准确。

This paper present a simple model to show the mechanisms that produce digital frequency dividers＇ aliasing effects. And we also get a relationship to determine the amplitude and location of the spurs and PM noise in the output frequency. With its aid, we can calculate the spurs and PM noise in the output signal of the PLL more accurately.