一种适用于VLSI实现的谐波电能计量算法

A Harmonic Energy Metering Algorithm Suitable for VLSI Implementations

提出了一种适用于超大规模集成电路(以下简称VLSI)实现的谐波电能计量算法。该算法以电网中能量的分布为出发点,对基波和谐波分量采用了不同的数字滤波处理,并且通过一个前馈控制系统实现了滤波器中心频率对电网频率的跟随,达到了同步采样的效果,解决了在电网频率不准确时快速傅里叶变换(以下简称FFT)频谱泄漏造成的计量误差问题。与用小波包分解实现谐波电能计量的算法相比,该算法需要的滤波器更少,更节省硬件面积,因而更适合VLSI的设计实现。网表级仿真结果表明电网频率在±5%范围内波动时基波有功功率计量误差小于0.1%,各次谐波有功功率计量误差小于1%,完全能满足谐波电能计量的商业要求。集成了该算法的谐波电能计量芯片已投片生产。

In this paper a harmonic energy metering algorithm suitable for very large scale integrated circuit （VLSI） implementation is proposed. By taking into consideration of the distribution of the energy, filters with different orders to process the fundamental and harmonics are used. All the digital filters can track the change of the fundamental frequency by a feed forward system. It solves frequency leakage （thus metering error） problem associated with frequency variations that fast Fourier transform （FFT） has. Comparing to the wavelet packet decomposition, the proposed algorithm is more area efficient because of fewer filters are needed. Simulations and hardware verifications show that a metering accuracy of 0.1% for the fundamental and of 1% for the harmonics even with the frequency varying by ±5% can be achieved. The algorithm is implemented in a chip that is currently in prototyping.