一种RS码编译码器的FPGA实现方法

FPGA-based Realization of a RS Encoder and Decoder

介绍了RS[255,223]编译码器的FPGA设计和基于线形反馈移位寄存器的编码器设计,以及由伴随式计算、关键方程求解、钱氏搜索、Forney算法等功能模块组成的译码器。为了实现简单高效的译码器,给出了一种改进的BM算法,该算法避免了求逆运算,提高了译码器处理速度及其硬件可实现性,并给出了仿真时序图。

This paper presents the design of RS [ 255, 223 ] encoder and decoder using an FPGA device, the encoder based on linear feedback shifting register, and the decoder consisting of functional blocks such as calculating the syndromes, solving the key equation, Chien searching and Forney algorithm. To design a simpler and more efficient decoder, an improved BM algorithm is given which involves no inversion operation thus improving the processing speed and the hardware realizability of RS decoder. The result of simulation is shown at the end of the paper.