基于可重构的高速并行数据采集系统的设计与实现

Design and Implementation of a Reconfigurable High-Speed Parallel Data Acquisition System

本文介绍了一种基于可重构技术的高速并行数据采集系统的设计方案及实现方法。系统每个采集通道由一组A/D和双端RAM组成,多个采集通道模块组成多通道全并行采集系统;采用Altera公司的现场可编程门阵列(FPGA)EP1C6-8和软核CPU为数据处理与控制核心,异步双端RAM为数据缓冲区,USB控制器为CY7C68013。采集系统使数据采集、数据处理、数据传输并行执行,同时系统具有较强的容错能力。本文描述了设计方案的硬件和软件实现,实验表明系统具有高速、实时、能耗低、容错强等特点。

The design and implementation of a high-speed parallel data acquisition system based on the reconfigurable technology is introduced. Each of the sample channels consists of a A/D and RAM model, and several channels compose the data acquisition system. Using the Altera＇s （FPGA） EP1C6-8 and CPU as the control core, an asynchronous double port RAM as the data buffer, CY7C68013 as the USB controller, and combining with the A/D model, the operations of data col- lection, data processing and data transfer are carried out in parallel , and the system has better ability of fault tolerance. The hardware and software implementation of the schemas are described in detail. The system has the advantages of high speed, real-timeness, and fault tolerance in the experiment.