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考虑热电耦合效应的全芯片温度特性优化方法 被引量：1

Full chip temperature optimization for considering thermal-electric coupling effects
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摘要 针对全局互连延时已成为制约电路性能的关键因素问题,提出了一种全芯片温度特性优化方法,使功耗和温度间的反馈在功耗模型与HotSpot软件结合运算数次后收敛,根据收敛结果确定优化方向.该方法同时考虑了延时、功耗和温度三者间的热电耦合效应.采用该方法对90 nm工艺的AMD Athlon64处理器进行仿真验证,结果表明,采用这种方法优化得到的芯片功耗和温度均有显著下降,芯片温度梯度也明显改善,芯片温度特性得到优化. Based on the fact that convergent results reflecting the feedback between power and temperature can be found by using the available power model and HotSpot software, a method is proposed for full chip temperature optimization. In the model, thermal-electric coupling effects among delay, power and temperature are taken into consideration. Simulations for the AMD Athlon 64 processor in 90 nm technology are given. Results show that the optimized chip temperature characteristics with lower temperature, decreased power and temperature gradients can be achieved.
作者 冷鹏 董刚 柴常春 杨银堂
机构地区 西安电子科技大学宽禁带半导体材料与器件教育部重点实验室
出处 《西安电子科技大学学报》 EI CAS CSCD 北大核心 2009年第6期1053-1058,共6页 Journal of Xidian University
基金 国家自然科学基金资助(60606006) 国家杰出青年基金资助(60725415) 重点实验室基金资助(9140C030102060C0303)
关键词 延时 功耗 缓冲器插入 热电耦合 delay power buffer insertion thermaleleetric coupling
分类号 TN405.97 [电子电信—微电子学与固体电子学]
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参考文献20

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共引文献5

同被引文献11

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引证文献1

西安电子科技大学学报
2009年 第6期

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