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先栅工艺中高K/双金属栅集成研究新进展 被引量：1

Latest Development of Integration of High-k/Dual Metal Gate in Gate First Process
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摘要 随着高K、金属栅材料引入到CMOS工艺,高K/双金属栅的集成已成为研究热点。利用多晶硅回刻和s杂结合两步全硅化工艺的方案,可实现低功耗和高性能电路的高K与双FUSI金属栅的集成。采用淀积-刻蚀-再淀积、双高K双金属栅的集成方案,也可实现高K与双金属栅的集成。为缓解费米能级钉扎效应,通过盖帽层或离子注入技术对高K或金属栅掺杂,可得到具有带边功函数的高K/双金属栅集成。多晶硅/金属栅复合结构为高K与双金属栅的集成提供了更灵活的选择。 With application of high-k and metal-gate materials in CMOS process, high-k/dual FUSI metal-gate became a hot subject. By using poly-Si etch-back combined with doping or deposition-etch-deposition process, high-k/ dual FUSI metal gate can be made for low-power and high performance circuit. In order to reduce Fermi-level pinning effect, capping layer or ion implantation could be used to realize high-k/dual-metal gate integration for circuits with band-edge work function. Moreover, high-k/dual metal gate process is compatible with poly-Si / metal gate structure.
作者 李永亮 徐秋霞
机构地区 中国科学院微电子研究所
出处 《微电子学》 CAS CSCD 北大核心 2009年第6期829-834,共6页 Microelectronics
关键词 高K材料 金属栅 费米能级钉扎效应 盖帽层 离子注入 功函数 High k material Metal Rate Fermi level pining Capping laver Ion implantation Work function
分类号 TN405 [电子电信—微电子学与固体电子学]
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参考文献33

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共引文献12

同被引文献13

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引证文献1

二级引证文献1

微电子学
2009年 第6期

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