多FPGA系统中自定义高速串行数据接口设计

Design of Custom High-speed Serial Peripheral Interface in Multiple FPGA System

为方便多FPGA系统中主从FPGA之间的命令与数据传输,节省连接的引脚数量,设计了一种基于FPGA的自定义高速串行数据传输模块。对主从串行模块进行了详尽的协议设计,得出了串行传输时序设计图,编写了verilog硬件代码并仿真通过硬件实测在25 MHz工作正常。该设计作为一个IP软核,略作修改后,可以被无缝整合到各种形式的嵌入式系统中。

The design of custom high-speed serial peripheral interface based on FPGA was introduced. It could be used in transferring instruction or data among principal and subordinate modules in multiple FPGA system . The detailed communication protocol was designed. The program was written with verilog HDL and simulated successfully. It works stably for 25 MHz in the reality testing. As an IP core, it could be transplanted to various forms of embedded systems after slightly modified.