摘要
维特比算法是卷积码的一种最大似然译码。维特比译码器中的存储部分,包括幸存路径的存储和路径度量的存储,其结构的选择对其占用硬件资源影响也不同。文章采用同址存储的方法来实现约束度为9的(2,1,9)维特比译码器中的幸存路径的存储,该方法相对于传统的寄存器存储、回溯法来讲,具有资源占用少、译码延时小等特点。同址存储是存储体的一种实现方法,较之别的存储方法,其优点是需要的存储单元较少。
The Viterbi algorithm is known to be an efficient method for the realization of maximum likelihood probability decoding of convolutional codes. And survivor path and path metric need to be stored. The different way of implementation can influence the performance of the decoder. In this paper, a plan of FPGA implementation of （2,1,9） Viterbi decoder using in-place updating in the survivor path memory management is proposed. Compared to traditional register- exchange and trace-back methods, it needs less memory and has less decoding delay.
出处
《计算机与数字工程》
2009年第12期42-46,共5页
Computer & Digital Engineering
