折叠式共源共栅CMOS LNA的优化设计

The Optimization Design of Folded Cascode CMOS LNA

基于TSMC 0.18μm CMOS工艺,采用折叠式共源共栅式结构,设计了工作于1.5GHz,电源电压为1.5V的低噪声放大器。采用此结构可以显著增大截止频率,从而可以改善噪声系数。本文主要从结构出发,均衡了噪声系数,阻抗匹配,增益以及线性度,并在ADS仿真平台上进行了优化与仿真模拟,在中心频率处,噪声系数为0.617 dB,增益S21为31.713dB,输入反射系数S11为-21.548dB,1dB压缩点为-11 dBm。其仿真结果与设计指标基本一致。

Based on the 0.18 μm CMOS technology, using the folded cascode structure, a low-noise amplifier operating in 1.5GHz and 1.5V supply voltage is designed. This structure can significantly increase the cut-off frequency, thereby improving the noise figure. Starting from the structure, balancing the noise figure, impedance matching, gain and linearity, and in the ADS simulation platform, the optimization and simulation are conducted in this paper, at the central frequency the noise figure is 0.617dB, gain S21 is 31.713dB, input reflection coefficient S 11 is 21.548dB, 1 dB compression is - 11 dBm. The simulation results are basically agreeing with the design targets.