CCD探测器的数字读出技术

Digital readout technique for CCD detectors

探测器的读出噪声是表征其性能的一个重要参数,它不仅限制了探测器的能量分辨,还影响探测器系统的动态范围。传统的CCD探测器信号读出部分都采用由模拟器件构成的相关双采样(Correlated Double Sampling,简称CDS)电路,这种方法已被证实能够有效抑制探测器噪声,但与此同时,由于CDS电路本身比较复杂,引入了新的噪声,它成为进一步减小读出噪声的一个屏障。为了消除模拟电路本身的噪声屏障,作者采用了一种基于高速ADC和FPGA的直接数字化读出方法,去除CDS电路,简化信号路径,由FPGA控制高速ADC对CCD探测器输出信号的参考电平和信号电平进行多次采样,用数值计算方法实现CDS功能,提高了信噪比,改善了探测器的性能。

Readout noise of CCD detector is an important parameter for charactering its performance. It restricts the energy resolution and affects the dynamic range of detector. Conventional readout techniques would bring new noises since the readout part of its correlated double sampling（CDS） circuit composed of many analog components, although it could effectively reduce readout noise. In this paper, a new technique based on high speed ADC and FPGA is presented. It removes the CDS circuit and simplifies the signal route. The reference voltage and signal voltage of CCD detector’s output are sampled many times by high speed ADC controlled by FPGA, and the digital CDS technique is realized with the numerical calculation method. The signal to noise ratio is increased, and the performance of the detector is improved.