基于FPGA的内建自测试的实现研究

Research for Built-In Self-Test Based on FPGA

针对大规模SOC芯片设计中BIST测试时间长和消耗面积大的问题,提出使用FPGA实现内建自测试的测试向量发生器、被测内核和特征分析器。通过Verilog HDL语言进行仿真,结果验证了所提方案的正确性和有效性。

A built-in self-test （BIST） methodology for testing inter-switch links of system on chip （SOC） is proposed, which can reduce both test time and test circuit area. An example is proposed to demonstrate BIST based on FPGA. Test pattern generator, circuit under test, character analysis system of built BIST were realized in one chip with FPGA. Then a simulation is performed on both the circuit. The result demonstrate the correctness and efficiency of proposed project.