ASIP编译器设计和实现

An ASIP compiler design and implementation

为了满足ASIP存储器约束和代码执行的实时性要求,提出一种同时考虑代码选择和寄存器分配的代码综合生成算法,同步处理代码生成的子问题。提出一种能描述ASIP寄存器复杂约束关系的数学模型;改进了传统的图染色算法,将寄存器分配问题转化为对有向数据相关图的简化问题。应用算法构造了一个编译器后端,测试表明,和传统的分步优化算法相比,降低了目标代码的空间尺寸,减少了寄存器溢出的几率。

A new code-generation algorithm which handles code selection and register allocation simultaneously is presented to satisfy register restriction of application specific instruction processors （ASIPs） and real-time requirement from applications. A model is presented to describe the complicated restrictions among registers of ASIP register file in this paper. The traditional graph-coloring algorithm is improved to be adapted to ASIP according to this model. The register allocation is translated into how to simplify this graph. At last the algorithm is applied to an ASIP compiler. Experimental results show it has better performance of code-generation and less register spilling than traditional code-generation algorithm.