基于VeriIog的单精度浮点数乘法器的设计与实现

Design and Implementation of Single-precision Floating Point Multiplier Based on Verilog

文章详细介绍了浮点数和浮点数乘法的原理,采用Verilog语言设计32位单精度浮点数乘法器。用Modelsim6.5进行了浮点数和实数之间的转换,使用Altera QuartusⅡ7.2,采用器件EP2S15F484C3,对乘法器进行了全编译和波形矢量时序仿真。将仿真结果转换为实数,与期望(真值)相比计算出乘法器的计算误差率,从而验证该设计的正确性和可行性。

The paper introduced the principle of the floating point numbers and the floating point multiplier, then designs 32-bit single-precision floating point multiplier based on Verilog. The software of Modelsim 6.5 is used for conversion of data format between floating point numbers and real numbers. The software of Ahera Quartus Ⅱ 7.2 is used for performing full compilation and the waveform vector timing simulation of the multiplier with EP2S15F484C3 device. In the end, the paper calculated the calculation error rate of the multiplier, compared with the expectations（ true value） after the simulation result was converted to real numbers, in order to verify the correctness and feasibility of the design.