期刊文献+

ASIC物理设计中金属层数对芯片的影响 被引量:2

Effect of Metal Layer on the Chip in ASIC Physical Design
下载PDF
导出
摘要 ASIC芯片物理版图设计的一个重要问题是选用几层金属层。以一款SMIC0.18μmDVBC芯片(BTV2040S03)为例,选用三种不同金属层工艺进行对比。首先设计出三种不同金属层的版图,分析电源电势分布判断其合理性;之后进行布线拥塞率的对比,以分析不同金属层工艺对布线的影响;最后通过最终布线的时序验证和最终流片结果来证实选用金属层设计的可行性。通过上述方法研究集成电路物理设计中,如何选择所使用工艺的金属层数,以达到最大限度节约芯片成本、减小芯片面积和满足布线及时序的目的。 One of the important problems of ASIC chip physical design is how many metal layers to be chosen. Three different metal layer technologies were compared based on the design of SMIC 18μm technology of digital video broadcasting cable chip. The layouts of three different metal layers were designed and the IR drop was analyzed to estimate the design rationality. Then the routing congestions were compared in order to analyze the effects on routing. According to the timing of routed layout and the final result of chip, the feasibility of the design was proved. This method can be used to research the choosing of the numbers of metal layer in order to save the costing, reduce the area and meet the routing and timing.
出处 《半导体技术》 CAS CSCD 北大核心 2010年第1期27-30,共4页 Semiconductor Technology
关键词 版图设计 金属层数 成本 面积 layout design metal layers costing area
  • 相关文献

参考文献3

  • 1BAKERRJ.CMOS电路设计、布局与仿真[M].第2版.北京:人民邮电出版社.2008:80-90.
  • 2程冲宽,喻文健,徐宁.超大规模集成电路互连线分析与综合[M].北京:清华大学出版社,2008:60-65.
  • 3王志功,景为平,孙玲.集成电路设计技术与应用[M].南京:东南大学出版社.2007.

共引文献1

同被引文献19

  • 1廖日坤,纪越峰,李慧.基于双核心处理架构的视频监控系统的设计[J].中山大学学报(自然科学版),2006,45(2):33-35. 被引量:2
  • 2张颖,潘亮.芯片版图面积的设计优化[J].中国集成电路,2006,15(7):57-60. 被引量:3
  • 3Chrisktober Saint;Judy Saint.集成电路版图设计[M]北京:清华大学出版社,2003.
  • 4Khosrow Golshan. Physical Design Essentials[M].Springer Science+Business,.
  • 5Synopsys. Synopsys Astro Workshop Lib Guide[M].Synopsys,2005.
  • 6HUANG L. Accelerated design convergence with IC com- piler-concurrent multi-mode, multi-corner ( MCMM ) and signoff driven closure [ R ] . TAIWAN : Synopsys Users Group, 2007.
  • 7Synopsys Inc. Using the synopsys design constraints for- mat application note version Z-2007. 03 [ R ]. Synopsys Inc, 2007.
  • 8WANG L T, WU C W, WEN X Q. VLSI test principles and architectures: Design for testability [ M ] . 2nd ed. San Francisco: Morgan Kaufmann, 2006.
  • 9STEIN M. Crossing the abyss: asynchronous signals in a synchronous world [J] . EDN, 2003, 48(16) :59- 69.
  • 10严天鸣,刘晓飞,蔡准.一种在MCMM条件下进行漏电功耗优化的有效方法[C]//SynopsysUsersGroupChina2014:深圳,2014:117-124.

引证文献2

二级引证文献3

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部