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5加数并行加法器及其进位接口

Parallel Adder with Five Addend and Its Carry Interface
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摘要 传统加法器在处理多操作数累加时,必须进行多次循环相加操作。针对该问题设计5操作数并行加法器及其高速进位接口。电路采用多操作数并行本位相加和底层进位级联传递的方式,在一定程度上实现多操作数间的并行操作,减少相加次数。模拟结果验证了该加法器的设计合理性,证明其能缩短累加时间、提高运算效率。 Traditional adder must do several times of cyclic addition operation in processing of multi-operand accumlation. Aiming at this problem, this paper designs a five addend parallel adder and its high speed carry interface. Because the circuit uses parallel own department addition of multi-operands and bottom layer carry cascade connection transmission mode, the parallel operation between multi-operands is realized and addition times are reduced. Simulation results verify the design reasonability of the adder and prove that it can shorten addition time, enhance operation efficiency.
作者 刘杰 易茂祥
机构地区 阜阳师范学院物理与电子科学学院 合肥工业大学应用物理系
出处 《计算机工程》 CAS CSCD 北大核心 2010年第1期251-252,259,共3页 Computer Engineering
基金 安徽省高校省级自然科学研究基金资助项目(2006KJ042B)
关键词 加法器 超前进位加法器 进位接口 adder Carry Look-Ahead Adder（CLAA） carry interface
分类号 TP342.21 [自动化与计算机技术—计算机系统结构]
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参考文献8

  • 1Sadrossadat S A, Amiri N K, Fakhraie S M. An Efficient Multi-operand Addition Structure[C]//Proc. of International Conference on Microelectronics. Cairo, Egypt: [s. n.], 2007: 73-76.
  • 2Komerup E Reviewing 4-to-2 Adders for Multi-operand Addition[CJ//Proc, of IEEE International Conference on Application- Specific Systems, Architectures and Processors. California, America: [s. n.], 2002: 218-229.
  • 3刘杰.多二进制数同步超前进位相加符号和溢出性研究[J].昆明理工大学学报（理工版）,2004,29(5):83-86. 被引量：4
  • 4Schulte M J, Chirca K. A Low-power Carry Skip Adder with Fast Saturation[C]//Proc. of the 15th IEEE International Conference on Application-specific Systems, Architectures and Processors. Galveston, TX, USA: [s. n.], 2004: 269-279.
  • 5Huang Yen-Mou, James B K. A High-speed Conditional Carry Select Adder Circuit with Asuccessively Incremented Carry Number Block Structure Forlow-voltage VLSI Implementation[J]. IEEE Trans. on Circuits and Systems, 2000, 47(10): 1074-1079.
  • 6Manzoul M A. Parallel CLA Algorithm for Fast Addition[C]//Proc. of Int'l Conf. on Parallel. Quebec, Canada: [s. n.], 2000: 55-58.
  • 7李云锋,赵金薇,周汇,俞军.一种基2冗余符号数加法的改进算法[J].计算机工程,2007,33(24):242-243. 被引量：1
  • 8张志伟,马鸿,李立健,王东琳.VLIW数字信号处理器64位可重构加法器的设计[J].计算机工程,2007,33(16):29-31. 被引量：1

二级参考文献13

  • 1Bedrij O.Carry Select Adder[J].IRE Trans.on Electronic Computers,1962,11(6):340-346.
  • 2Hwang Kai.Computer Arithmetic-Principles,Architecture and Design[M].John Wiley and Sons Inc.,1979.
  • 3Kogge P M,Stone H S.A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations[J].IEEE Trans.on Computers,1973,22(8):786-793.
  • 4Brent R,Kung H T.A Regular Layout for Parallel Adders[J].IEEE Trans.on Computers,1982,31(3):260-264.
  • 5Schmookler M S,Putrino M,Roth C,et al.A Low Power High Speed Implementation of a PowerPC Microprocessor Vector Extension[C] //Proc.of the 14th Arithmetic Conf.,Adelaide,Australia.1999.
  • 6Patterson D A,Hennessy J L.Computer Architecture:A Quantitative Approach[M].3rd ed.Beijing:China Machine Press,2002.
  • 7Avizienis A. Signed-digit Number Representations for Fast Parallel Arithmetic [J]. IRE Trans. on Electronic Computers, 1961, 10(1 ).
  • 8Parhami B.Generalized Signed-digit Number Systems:A Unifying Framework for Redundant Number Representations[J].IEEE Transactions on Computers,1990,39(1):89-98.
  • 9Quach N,Takagi N,Flynn M.On Fast IEEE Rounding[R].Computer System Laboratory,Dept.of EE and CS,Stanford Univ.,Technical Report:CSL-TR-91-459,1991.
  • 10Kawahito S,Kameyama M,Higuchi T.Multiple-valued Radix-2 Signed-digit Arithmetic Circuits for High-performance VLSI Systems[J].IEEE Journal of Solid-State Circuits,1990,25(1).

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计算机工程
2010年 第1期

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