基于FPGA实现的数字钟设计

Digital clock design based on FPGA

为了提高开发的效率,缩短其开发的时间,设计师逐渐转向可编程逻辑器件的开发。文章介绍了应用FPGA采用自顶向下的方法来设计数字钟的方案。设计时,首先用VHDL语言编写各个功能模块,分别在QuartusⅡ开发环境下编译、仿真,然后再用顶层文件将各功能模块连接起来,最后在实验箱上进行测试,证实该设计方法切实可行。

In order to enhance the development efficiency and reduce its time, designers gradually turn their attentions to the development of programmable logic devices. This paper introduces the application of FPGA, uses top-down method to design digital clock. When designing, it first uses the VHDL language to edit each functional module, separately compiles and simulates under Quartus Ⅱ, then uses the top-level document to connect all functional modules, finally carries on the test in the experiment box, confirms that this design method is practical and feasible.