基于VITAL语言的FPGA板级仿真验证研究

Simulation and Verification of VITAL-based FPGA System

数字电路在投产前的功能验证工作至关重要。随着器件工艺的进步,单片FPGA上集成的功能越来越复杂,按照改进样机的流程开发,应用FPGA芯片的电子系统时,在产品上市时间和产品开发费用等方面逐渐超出设计者的预算值;而仿真验证方法是由仿真程序,如ModelSim,载人板上元件的模型信息、布局和互连信息,并在激励文件作用下产生系统输出的虚拟验算方法,具有省时,成本低、调试方便和有利于升级换代等优点。介绍用于元件建模的VITAL语言的基本规则及其描述电路模型的基本方法,应用FPGA的快速比较网络的仿真结果表明,仿真验证方法可以有效地提高FPGA系统功能、时序验证的效率。

Verification of digital circuits is a significant issue because the fabrication process progresses rapidly from very large scale integrated circuit to system on chip. Traditional method of design verification is prototyping. It＇s obviously expensive and can not be adapted to the reduced time to go on the market when developing FPGA - based prototype again. Simulation attempts to create a virtual prototype by collecting information about the components, it has the virtue of independent technology and easier debugging. The paper introduced VITAL and the way to model component with VITAL. Research status of board - level verification of FPGA and its prerequisite and procedure are discussed, and experiment results show the validity of the method. The work plays a part in generalizing domestic VITAL - based board - level verification of FPGA.