基于FPGA的内建自测试的实现研究

Research for Built-In Self-Test Based on FPGA

内建自测试技术源于激励-响应-比较的测试机理,信号可以通过边界扫描传输到芯片引脚,因而即使BIST本身发生故障也可以通过边界扫描进行检测;为了解决大规模SOC芯片设计中BIST测试时间长和消耗面积大的问题,提出了一种用FPGA实现BIST电路的方法,对测试向量发生器、被测内核和特征分析器进行了研究;通过对被测内核注入故障,然后将正常电路和注入故障后的电路分别进行仿真,比较正常响应和实际响应的特征值,如果相等则认为没有故障,否则发生了特定的故障;利用ModelSim SE 6.1f软件仿真结果表明了该方法的正确有效性和快速性。

BIST technology comes from the test mechanism of stimulus-- respond--compare, signal of BIST can be transmitted to chip pin by scan test, so even if BIST itself breaks down also can be measured. A built--in self--test （BIST） methodology for testing inter--switch links of system on chip （SOC） is proposed, which can reduce both test time and test circuit area. An example is proposed to demonstrate BIST based on FPGA. Test pattern generator, circuit under test, character analysis system of built BIST were realized in one chip with FPGA. Then a fault is injected into a normal circuit, and then a simulation is performed on both the normal circuit and the circuit with fault injection. Comparing the characteristic value which is re- sponded normally and the value which is under tested actually, if the two values are equal, there is not trouble, otherwise the specific trouble takes place. ModelSim SE 6. if software have indicated this method is correct, effective and fast.