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一种基于可测性和低功耗的高层次综合方法

High-level synthesis method based on testability and low power
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摘要 提出了一种基于遗传算法的多目标优化高层次综合方法。该方法在时间和面积约束下,通过高层次调度和模块分配,对可测性和功耗问题进行研究。给出一种可同时进行调度和模分配的编码方法,并设计了相应的遗传算子,避免了进化过程中不可行解的产生。实验证明了该方法在可测性改善和功耗优化方面的有效性。 This paper proposed a high-level synthesis method for multi-objective optimization based on genetic algorithm. This method studied the testability and power problems through high-level scheduling and module allocating under time and area constrained. The main contributions were that it proposed a novel coding method could be used for scheduling and module allocating simultaneously and designed corresponding genetic operators avoiding the generation of infeasible solutions. The efficiency of testability improvement and power optimization is demonstrated by experimental results.
作者 孙强
出处 《计算机应用研究》 CSCD 北大核心 2010年第1期167-169,173,共4页 Application Research of Computers
基金 国家自然科学基金资助项目(60273081)
关键词 高层次综合 可测性 遗传算法 调度 模块分配 high-level synthesis testability genetic algorithm scheduling module allocating
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参考文献9

  • 1HERMANANI I4, SALIBA R. An evolutionary algorithm for the testable allocation problem in high-level synthesis [ J ]. Circuits Syst Comput, 2005,14 (2) :347- 366.
  • 2SUN Qiang, ZHOU Tao, L1 Hai-jun. A novel register allocation algorithm for testability [ J ]. Tsinghua Science and Technology, 2007,12(Sl ) :57-60.
  • 3SAFARI S, JAHANGIR A H, ESMAEILZADEH H. A parameterized graph-based framework for high-level test synthesis[J]. Integration, the VLSI Journal, 2006,39(4) :363-381.
  • 4温东新,杨孝宗,王玲.一种VLSI高层综合低功耗设计方案及实现[J].计算机研究与发展,2007,44(7):1259-1264. 被引量:8
  • 5WANG Ling, JIANG Ying-tao, SELVARAJ H. Scheduling and optimal voltage selection with multiple supply voltages under resource constraints [ J ]. Integration , the VLSI Journal, 2007,40 ( 2 ) : 174- 182.
  • 6KUMAR A, BAYOUMI M, ELGAMEL M. A methodology for low power scheduling with resources operating at multiple voltages [ J ]. Integration, the VLSI Journal, 2004,37( 1 ) :29-62,.
  • 7HARIYAMA M, AOYAMA T, KAMEYAMA M. Genetic approach to minimizing energy consumption of VLSI processors using multiple supply voltages[J]. IEEE Trans on Computers, 2005,54(6) :642- 650.
  • 8HARMANANI H, AOUNI H. An incremental approach for test scheduling and synthesis using genetic algorithms [ C ]//Proc of the 2nd IEEE NEWCAS. 2004:69-72.
  • 9MIKE T C L. High-level test synthesis of digital VLSI circuits [ M ]. Norwood, MA: Artech House, 1997.

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