NCL电路并行处理结构研究

Research of NCL circuits parallel processing architecture

针对NCL电路数据编码方式的特点,提出了一种并行数据处理的NCL电路结构,通过同时对两路双轨编码数据流的并行处理,提前计算出下一个无效数据,缩短了无效数据维持时间。此结构应用到4×4乘法器的设计,采用COMS0.18μm工艺,乘法器在非流水模式下和2级流水模式下分别进行了综合、布局布线和仿真,与传统NCL4×4乘法器相比,无效数据维持时间分别缩短了32.9%和33.2%。

This paper proposes a framework of NCL circuits parallel processing for reducing the NCL data wave time.After the two dual-rail data waves through the parallel circuits,the next null data has been calculated,so,the data to data cycle time has been shortened.Taking the 4×4 multiplier for example,the circuits have been fabricated in 0.18 μm CMOS process.In the case of non-pipelining module,TDD has reduced 32.9% and in the case of 2 stage pipelining module,TDD has reduced 33.2%.