基于FPGA的UART通信接口设计与实现

A Design to Implement UART Interface of Communication Based on FPGA

通用异步接收发送器在嵌入式系统设计以及SOC设计中得到了广泛的应用。介绍了一种以状态机控制为核心、波特率可调整的UART通信接口在FPGA上实现的方法。设计利用Verilog HDL描述完成设计,进行了多种波特率的功能测试,最后给出了FPGA上的综合实现与验证仿真,仿真和综合结果显示整个设计正确、可靠。设计可经过简单修改形成IP核直接移植至系统设计中,提高了设计效率。

Univesal asynchronous receiver and transmitter are widely used in embedded system and SOC. A novel of a method to implement UART based on Field Programmable Gate Array（FPGA） was presented. The hard core of the design is controlled by finite state machine （FSM） and the baud rate is adjustable. The design with Verilog HDL was presented. The simulations and the configuration on FPGA were provide. The result of emulations and synthesis show that the whole design is valid an reliable. The design can form IP core by A simply modification and transplant to systerm design to improve design efficiency.