摘要
本文介绍一种与MSP430兼容的16位低功耗微处理器的设计,面向医疗助听器应用提出一种新型结构,采用Verilog语言设计,通过FPGA实现硬件功能验证,并使用Synopsys公司的EDA工具进行仿真、综合、功耗分析和版图实现。内核单周期指令的功耗在100pJ左右。
A design of 16-bit low-power microprocessor,which is compatible with MSP430,is presented in the paper.A new structure for medical hearing aid is designed with Verilog.Function of this design is verified by FPGA.The design is simulated,synthesized and analyzed.The layout is designed by using the EDA tools of Synopsys.Power of the single circle instruction of the core is about 100pJ.
出处
《微计算机信息》
2010年第2期161-163,共3页
Control & Automation
