基于FPGA多级分布式算法的FIR数字滤波器的设计

The Design of Multi-Channels Distributed Arithmetic Algorithm FIR Filter Based on FPGA

目的实现多级分布式算法,设计滤波器以提高运算速度,节省资源.方法多级分布式算法采用串并结合的方式实现,从底层到顶层逐级构建数字系统,通过查表法完成基于多级分布式算法的FIR滤波器设计,使用QuartusII自带的仿真软件对系统进行仿真,并将滤波器输出结果导入Matlab进行功率谱分析.结果在FPGA上实现了FIR数字滤波,由功率谱密度曲线分析,测试信号经FIR滤波器滤波后,高频分量对低频分量的衰减可达到23dB,很好地抑制了带外频谱.达到与传统FIR滤波器同样的滤波效果.结论基于FPGA多级分布式算法的FIR数字滤波器具有良好的滤波效果,其设计方案具有可行性.

In order to design a FIR digital filter on a FPGA chip, which can realize the same processing result by contrast with the traditional FIR filter, a novel multi-channels distributed arithmetic algorithm is presented. Multiplication operation is achieved by bit shift, with the purpose of saving lots of resources in chip of FPGA. The multi-channels distributed arithmetic algorithm combines serial mode with parallel mode. The digital system is built from bottom level to top level gradually. And the design of multi-channels distributed arithmetic algorithm based FIR filter is achieved in look-up table method. The simulation software embedded in Quartus II is used to run simulation for the designed system. Then the simulation results of FIR filter are imported into MATLAB to generate power spectrum curve. To analyze the power spectrum, we can find that the least attenuation of high frequency versus low frequency is up to 23dB ,the out-band spectrum is restrained well. The multi-channels distributed arithmetic algorithm FIR filter based on FPGA can realize the expectant results. The feasibility of distributed arithmetic algorithm is proved adequately.