高动态GPS接收机跟踪环路设计与实现

Design and Implementation of High Dynamic GPS Receiver Tracking Loop

为了解决高动态环境下GPS信号跟踪问题,讨论了跟踪环路类型和参数的选择策略,给出了一组适合高动态应用的环路参数,分析了基于开环频率估计和2阶FLL(Frequency Lock Loop)辅助3阶PLL(Phase Lock Loop)的高动态环境下快速的捕获转跟踪方法,给出了在由FPGA和DSP组成的硬件平台上的具体实现,利用GPS信号模拟器对所设计的跟踪环路的动态性能进行了验证。测试结果表明所设计的高动态跟踪环路能够承受60g视距动态应力。

In order to solve problems such as tracking GPS signal under high dynamic situation,the tracking loop type and parameters are discussed and then a set of suitable parameters are given.An open loop frequency estimator and a 3rd-order PLL （Phase Lock Loop） assisted by 2nd-order FLL （Frequency Lock Loop） are used to speed up transition from signal acquisition to signal tracking.The hardware implementation based on FPGA and DSP is described.Finally the tracking loop s dynamic ability is evaluated using GPS signal simulator.The result shows that it can work well under dynamic stress with 60g line-of-sight acceleration.