LDPC码译码算法的C语言FPGA编程实现

Decoding Algorithm of LDPC Codes Based on FPGA Programming in C Language

结合低密度奇偶校验码(LDPC)的译码算法和最新的现场可编程门阵列(FPGA)技术,提出了一种对低密度奇偶校验码的最小和算法(MSA)进行C语言现场可编程门阵列编程实现的新方案。基于Xilinx公司的Virtex2系列芯片XC2V2000,设计实现了一种码长为250,码率为0.5的(3,6)低密度奇偶校验码译码器,并给出了寄存器传输级(RTL)协同仿真系统结构,证实了低密度奇偶校验码具有良好的纠错性能,为软件工程师开发基于现场可编程门阵列的嵌入式系统提供了新的思路。

A novel method is proposed, which implements min sum algorithm （MSA） of low-density parity （LDPC） codes based on field programmable gate array（FPGA） programming in C language. A （3,6） LDPC decoder a code rate of 0.5 and a block size of 250 bits is implemented on the basis of Xilinx＇ s Yirtex2 series check with chip XC2V2000. The Register Transfer Level （RTL） simulation structure is given and the good performance of error correction is verified. A new idea is provided for soft engineers to develop embedded systems based on FPGA.