摘要
针对实验室的差分电容变化量为fF量级、频带宽度为0-20kHz的电容式加速度计,设计了一种可以有效减少噪声、失调电压和寄生电容影响的读出电路。该电路由开关电容积分电路、低噪声运放和单位增益采样保持电路组成。在0.5μm 2P3MCMOS工艺下完成该电路设计,通过仿真结果表明,该电路的输出电压与差分电容变化量成很好的线性关系,可以检测差分电容变化量达到fF量级。
According to our lab＇s capacitive accelerometer which has differential capacitance output in the fF range and a bandwidth of 20kHz, a readout ASIC with substantially lower noise, offset voltage and higher immunity to parasitic capacitance is designed. This circuit is composed of switched-capacitor integrator circuit, low noise amplifier and unitygain sample-and-hold circuit. This design implemented 0.5μm 2P3M CMOS process. Simulation shows good linearity between input differential capacitance and output voltage. Besides, differential capacitance in the fF range can be detected.
出处
《仪表技术》
2010年第1期12-14,共3页
Instrumentation Technology
基金
国家自然基金资助项目(60871037)
863计划资助项目(2007AA04Z341)
关键词
电容式加速度计
读出电路
开关电容积分电路
低噪声运放
采样保持电路
capacitive aecelerometer
readout circuit
switched-capacitor integrator circuit
low noise amplifier
sample-and-hold circuit
