摘要
峰值检测是数字存储示波器的重要技术之一,用来实现波形毛刺的捕捉,包络显示和限制混叠3个功能。用VHDL语言编程设计了峰值检测模块,采用流水线思想,实现了峰值检测功能。该模块在实际项目中得到验证,可以捕获20 ns以上的毛刺信号。创新点在于采用FPGA作为实现示波表峰值检测模块的器件,目的在于提高峰值检测的速度,减轻MCU的负担,改进了峰值检测的指标。
Peak detect is one of the important technique of the digital storage oscilloscope. So it' s widely used in deburring waveform capture, displaying envelope and aliasing limit. VHDL language is used to program into FPGA to design the block of peak detect. Based on the way of pipeline, the peak detection is achieved. The module has been verified in actual project, it can catch more than 20 ns glitch signal. Innovation of this design is that FPGA is used as the device of realizing peak detect to increase speed of peak detect, decrease work of MCU, and improve the indicator of peak detect.
出处
《测控技术》
CSCD
北大核心
2010年第1期10-12,共3页
Measurement & Control Technology