一种高层次低功耗综合设计方案及实现

A High-level and Low Power Consumption Synthesis Scheme and its Implementation

提出一种在时间约束条件下的高层次低功耗综合设计方案,该方案综合考虑多电压调度和资源绑定技术,实现优化电源电压和降低电路开关活动性的目的.并且方案在调度过程中考虑了调度对绑定的影响,这样的结果更利于绑定,能更大限度地降低功耗.所提出的算法已用C语言实现,算法的时间复杂度为O(n2),其中n为数据流图中节点的数目.并将算法应用于3个基准电路,功耗平均优化为36.6%.实验结果表明:此算法具有较好的功耗优化能力和较低的时间复杂度.

In this paper, a high level synthesis scheme based on multiple voltages scheduling and resource binding is proposed for low power design. In this scheme a simultaneous optimization method of multiple voltages scheduling and resource binding is proposed to optimize power dissipation through optimizing power supply voltage and switching activity under timing constraints. The proposed scheme is characterized with taking the influence of scheduling into consideration of binding in the scheduling process, resulting in more conducive contribution to binding, and further reducing the power consumption. The proposed algorithm is implemented in C environment and is found to have time complexity of O（n2）, where n is the number of nodes in the data flow graph. Experiments with three benchmarks indicate that the proposed algorithm achieves the power reduction by an average of 36.6% with high power optimizing index and low timing complexity.