基于FPGA的同步动态随机存储器测试仪的实现

SDRAM Tester Design Based on FPGA

针对动态同步存储器在高速运行时出现的读写错误,设计了一种自动测试仪,允许自动改变电压,自动调整同步内存的参数,通过大量数据读写内存来确定故障芯片对哪种参数比较敏感,从而确定测试方案。

This article mainly discusses how to design SDRAM tester, which can read, write and compare the mass data, regulate the working voltage and the SDRAM parameter automatically, in order to know which parameter the failure chip is sensitive to.