摘要
将数据挖掘方法用于数字集成电路规律性提取,提出了一种扇形结构模板的规律性提取算法.采用压缩式存储及删除缓冲器结构等方法,降低了电路的存储空间.通过边权值编码,实现了逐级产生扇形频繁子电路的算法,解决了传统算法对大规模数字集成电路规律性提取时间复杂度过高的问题.实验结果表明该算法比SPOG与TREE算法更能充分提取电路的规律性,规律性提取时间更短.
By using the method of data mining in the extraction of functional regularity in digital ICs,a novel template called FAN generation algorithm is proposed.To save the memory,a more efficient compressed storage strategy and deleting the buffer structure method are used when dealing with very large scale ICs.With the weights of edges are encoded,an algorithm which used to generating fan-like frequent subcircuits gradually is proposed,therefore,the problem of high complexity during the extraction of functional regularity in very large scale ICs has been solved effectively.Experimental results show that this fan-like template algorithm is more effective and can obtain a better circuit covering result faster than the SPOG and TREE methods.
出处
《电子学报》
EI
CAS
CSCD
北大核心
2010年第1期199-203,共5页
Acta Electronica Sinica
基金
国家重大基础研究项目(No.61398)
关键词
频繁子电路
数据挖掘
规律性提取
规则性系数
frequent subcircuits data mining regularity extraction regularity index