一种基于Farrow滤波器的并行采样时间误差校正

A sample-timing error calibration for time-interleaved ADC based on Farrow filter

用Farrow结构滤波器对并行采样信号进行时间误差校正,通过DSPBuilder软件将设计的滤波器模型转化为硬件语言,利于FPGA实现。此方法在时间误差改变的情况下也无需改变滤波器系数,易于实时校正,适用范围宽广。随着过采样倍数的增大或滤波器阶数的增加,校正后信号无杂散动态范围SFDR提升幅度增大。实验结果表明该方法能有效抑制时间误差所引入的杂散频谱,提高信号的无杂散动态范围,具有较高可行性。

This paper discussed a method which uses Farrow filter digital technology to calibrate the Sampie-timing errors, transforms the filter model into hardware verilog by DSPbuilder software, easy to use in FPGA. This method needn＇t to change filter coefficients even if time-error is different, it can calibrate error timely and use widely. Along with the ratio of sample frequency and signal frequency or exponent number of filter increases, the rate of increase of signal＇s SFDR is enhanced. The experimental results show that the method can restrain the spurious spectrum introduced by the time error and effectively enhance the signal spurious-free dynamic range, has high feasibility.