基于CdV/dt现象分析的功率MOS管建模

Modeling of power MOSFET for analysis of CdV/dt induced effects

为了改善功率MOS管及其驱动电路在高频开关状态下,功耗与可靠性等性能上的恶化问题,分析了此类电路中由于CdV/dt现象所导致的寄生效应.首先考虑功率MOS管及驱动电路的主要寄生参数,详细分析了CdV/dt现象产生的机理.在此基础上,采用状态方程的建模方法,提取关键电压与电流参数作为状态变量,建立并有效验证了一种功率MOS管的数学分析模型.通过对此模型的仿真,发现CdV/dt现象会带来栅极耦合电压、穿通电流、漏极振荡等不良寄生效应.同时对各种寄生参数与效应间的关系进行了分析.最后,根据仿真分析结果,给出了电路的优化设计方法.实际电路的测试结果证明,该功率MOS管模型与驱动电路的优化方法在CdV/dt现象分析与改善上具有明显作用.

Under high switching frequency conditions, in order to improve the performances of power loss and reliability of power metal oxide semiconductor field effect transistor （MOSFET） and its driving circuits, the CdV/dt induced parasitic effects are analyzed. Considering main parasitic pa- rameters of the devices and driving circuits, the switching operation process to generate CdV/dt induced effects are discussed in detail firstly. Then, by using the equations of state and selecting criti- cal state variables, an analytical power MOSFET model is deduced and validated. The simulations of this model show several CdV/dt induced parasitic effects, such as induced gate voltage, shoot- through current and drain voltage oscillations. The relations between these effects and different values of parasitic parameters are studied also. Finally, according to the simulation results, the design optimizations of the circuits are presented. The experimental results show that the proposed power MOSFET＇ s model and circuits＇ design optimizations have obvious effects on the analysis and improvement of CdV/dt induced parasitic effects.