深亚微米下芯片后端物理设计方法学研究

IC physical design methodology research under DSM

随着摩尔定律的发展,90/65nm工艺下的大规模芯片越来越多,后端物理设计变得更加复杂,遇到了很多新问题,如高集成度、层次化设计、泄漏功耗、多角落-多模式、串扰噪声等,签收的标准也发生了变化。因此必须改进物理设计方法学,适应新的情况,来取得流片成功。

Now IC industry has come to 90/65nm process node. The physical design flow becomes more complicated, with many new problems emerging, such as high cell density, hierarchical design flow, leakage power, multi-corner multi-mode, crosstalk noise, etc. The tapeout signoff criterion have changed a lot. So the physical design flow must be updated to ensure the first-silicon success.