期刊文献+

多核之间光互连技术的研究 被引量:1

A Study of Optical Interconnects Technology in Multi-core Architectures
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摘要 随着集成电路技术的发展,单个芯片上核的数目不断增加,多核将成为芯片体系架构的未来发展趋势。核间的互连成为芯片设计中的一个关键技术。传统的片上电互连在带宽、时延、能耗和可靠性等方面都面临挑战,光互连可以很好地解决这些问题。本文对现有片上光互连的集成光电子器件发展进行了综述,在此基础上研究了一个典型的多核光互连系统,对网络结构、节点组成和通信过程等逐一进行了分析。结果表明,光互连是未来多核系统的有效互连方式。 The development of integrated technology enables more and more cores to be incorporated into a single chip. Multi-core archtictures will be the main thrust driving the evolution of the chip design. Interconnects play a significant role in chip design. Traditional on-chip electrical interconnects face hard challenges in bandwidth, latency, power consumption and scalability. Optical interconnects can be a solution, increasing communication bandwidth and decreasing latency. This paper summarizes the development of current integrated opto-electrical components related to optical interconnects on chip, and studies a typical muli-core architecture with optical interconnects. The network structure, nodes architecture and process of communication are analyzed in details. Finally, the results show that optical interconnects will be the efficient approach of multi-core architectures in the future.
作者 李慧 顾华玺
出处 《中国集成电路》 2010年第2期50-55,共6页 China lntegrated Circuit
基金 国家自然基金项目(No.60803038) 国家重点实验室专项基金(No.ISN090306)
关键词 多核 光互连 集成光电子器件 Multi-core, Optical Interconnects, Integrated Opto-electrical Component
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参考文献16

  • 1Borkar, S. Thousand Core Chips-A Technology Perspective. in DAC. USA: ACM. 2007.
  • 2Horowitz, M. and W. Dally. How scaling will change processor architecture, in Solid-State Circuits Conference,Digest of Technical Papers. ISSCC. 2004 IEEE International. 2004.
  • 3Agarwal, A. and M. Levy. The KILL Rule for Multicore. in Design Automation Conference, 2007. DAC '07.44th ACM/IEEE. 2007.
  • 4Geer, D., Chip Makers Turn to Multicore Processors. ( Industry Trends ).2005.
  • 5Dally, W.J. and B. Towles. Route packets, not wires: on-chip interconnection networks, in Design Automation Conference. 2001.
  • 6Hemani, A., A. Jantsch, S. Kumar, A. Postula, J. Oberg, M. Millberg, and D. Lindqvist. Network on a Chip: An architecture for billion transistor era. in Proc. IEEE NorChip Conference. 2000.
  • 7Benini, L. and G. De Micheli, Networks on chips: a new SoC paradigm. Computer, 35 ( 1 ) : p. 70-78.2002.
  • 8Jantsch, A. and H. Tenhunen, Networks on Chip. Kluwer Academic Publishers. 2003.
  • 9Srivastava, Scaling Analysis N. of and K. Banerjee. A Comparative Metallic and Carbon Nanotube Interconnections for Nanometer Scale VLSI Technologies. in the 21st International VLSI Multilevel Interconnect Conference ( VMIC ). 2004.
  • 10Joshi, A., Shamim, K. Batten, K Asanovic, Yong-Jin and V. Beamer, I Stojanovic. Silicon-photonic clos networks for global on-chip communication, in 3rd ACM/IEEE International Symposium on Networks-on-Chip. 2009.

同被引文献11

  • 1乔保军,石峰,计卫星.多核处理器核间互连的新型互连网络[J].北京理工大学学报,2007,27(6):511-516. 被引量:6
  • 2Shen J P, Lipasti M. Modern Processor Design[ M ].北京:清华大学出版社,2007.
  • 3Patterson D A, Hennessy J L.计算机组成与设计[M].郑伟民,译.北京:机械工业出版社,2007.
  • 4Zhang Y P,Jeong T. A Study. of the On-chip Interconnection Network for the IBM Cyclops64 Multi- core Architecture [ C ]//Proceedings of 20th IEEE International Parallel Distrib- uted Processing Symposium. [ s. 1. ] : [ s. n. ] ,2006 : 1 - 10.
  • 5Culler D E,Singh J P, Gupta A.并行计算机体系结构[M].第2版.李晓明,译.北京:机械工业出版社,2002.
  • 6Ravankar A A, Sedukhin S G. "Mesh-of-Tori" :A Novel In- terconnection Network for Frontal Plane Cellular Processors [ C]//Proceedings of IEEE First International Conference on Networking and Computing. [ s. 1. ] :[ s. n. ] ,2010:281-284.
  • 7Haroon-Ur-Rashid Khml, Shi Feng,Jia Xinli. Performance of Triplet Based Interconnection Strategy for Multi-core On-chip Processors[ C ]//IEEE International Conference on High Per- formance Computing and Communications. [ s. t. ] : [ s. n. ], 2009 : 163-170.
  • 8胡晨骏,王晓蔚.基于多核集群系统的并行编程模型的研究[J].计算机技术与发展,2008,18(4):70-73. 被引量:6
  • 9王炜,汤志忠,乔林.片上多处理器互连技术综述[J].计算机科学,2008,35(9):7-8. 被引量:7
  • 10卜凡,赵忠民.64位多核CPU中交叉开关总线的设计与实现[J].计算机与数字工程,2008,36(11):151-154. 被引量:1

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