LPC IP核的设计和应用验证

The Design and Application Verification of LPC IP Core

本文主要介绍了一种LPC核的设计,按LPC(Low Pin Count)总线协议设计,具有模块化、兼容性和可配置性,适用于SOC芯片集成。通过实现一个配置寄存器,使LPC核具有可配置性。功能仿真的结果表明LPC核能够满足设计要求以及功能的正确性。

This paper presents a design of LPC IP core. According to the LPC （ Low Pin Count） bus communication, this core has the characteristic of modularity and confgurability, and is ideal for SOC （ System On a Chip） application. This LPC core has configurability because of a configure register. The result of the simulation has shown the correctness of the function of the LPC core.