摘要
基于功能级处理器模拟器,采用时序制导的方法,提出了一种时钟级处理器模拟器的快速开发方法。该方法对指令的模拟引入流水线,依靠流水线的时序推动功能模块的运行,如ALU、Co-processor、MMU、TLB等。给出了RISC/MIPS流水线的设计方法,并进一步阐述了如何将流水线和处理器功能级模拟单元的耦合起来,构成时钟级模拟的整体框架。基于此框架,开发了ClkSim模拟器。经过SPEC CPU 2000的对比测试,ClkSim拥有较高的模拟性能和精度。
A fast implementation of cycle-level processor simulator is introduced,which is based on function-level processor simulator,with timing-directed method involved.This method uses an instruction pipeline to drive function module of processor simulator work,such as ALU, Co-processor,MMU, and TLB.Tbis paper presents the design of a classic pipeline of RISC/MIPS instruction set,and how to integrate the pipeline and function module of processor simulator,to generate a cycle-level processor simulator framework.The tests of SPEC CPU 2000 prove that,this cycle-level processor simulator has high accurate and performance.
出处
《计算机工程与应用》
CSCD
北大核心
2010年第6期63-66,70,共5页
Computer Engineering and Applications
基金
国家自然科学基金(No.60633040)
国家高技术研究发展计划(863)(No.2007AA01Z115)~~
关键词
功能级
时钟级
时序制导
处理器模拟
function-level
cycle-level
timing-direct
processor simulator
