一种循环流水阵列架构

A pipelined loop array architecture

描述了一种基于循环流水计算的阵列架构(PLAA),该阵列架构能够工作在基于AHB协议的总线接口上,通过与ARM处理器指令通信,达到辅助主处理器进行大规模密集计算的目的。描述了这一处理器的结构,并着重介绍了二维DCT算法在PLAA中的映射与实现。仿真结果显示,PLAA能达到7倍以上于通用处理器的性能,并在实现复杂度、运行效率与通用性中达到一个权衡。

This paper describes a reconfigurable array architecture based on pipelined loop computing. That is, the array processor communicates with the main processor through the AMBA interface. The paper introduces the architecture of PLAA especially 2D-DCT arithmetic implementation. The simulation results show that PLAA can achieve seven times or much higher performance than general processor, and make a balance among complexity, performance and compatibility.