基于SOPC的边界扫描测试控制器IP核设计

Design of IP Core for Boundary-Scan Test Controller based on SOPC

在研究边界扫描数字电路测试技术标准IEEE1149.1的基础上,采用SOPC设计技术,用FPGA设计实现了一款基于Avalon总线的边界扫描测试总线控制IP核,与其它复用IP核可形成以NIOS Ⅱ处理器为核心的通用数字电路边界扫描测试控制器,该控制器产生符合IEEE1149.1标准的测试信号控制被测边界扫描系统,进行各种边界扫描测试;该IP核的成功设计,为基于边界扫描的电子系统机内自测试系统的实现,奠定了坚实的应用基础。

According to the IEEE Std 1149.1 and the SOPC technology, a kind of boundary-scan test bus controller IP core is designed, based on Avalon bus. Together with some reusable IP Cores, it can be used to construct a universal boundary-scan test controller with NIOS II CPU, which is used for digital circuit test. The design of the IP core provides a basis for the realization of Built in Test system based on Boundary Scan.