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基于AltiVec技术的浮点乘加单元的设计

Design of Floating-Point Multiply-Add Fused Unit Based on AltiVec Technology
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摘要 Alti Vec技术是为提高PowerPC的向量处理能力而对PowerPC指令集体系结构的扩展;浮点乘加单元是向量处理单元的主要构成部分,设计一种基于Alti Vec技术的向量浮点乘加单元;在基本浮点乘加器的基础上,提出了java模式下对非规格化数的预规格化处理;设计采用了一种半并行的结构,与传统的全并行结构相比可以节省一半的硬件面积;时钟频率为266 MHz时,java模式下5拍可以完成,非java模式下4拍可以完成。 AltiVec technology is an extension to the PowerPC Instruction Set Architecture to enhance the performance in vector process- ing. Floating-point multiply-add fused (MAF) unit is a main component of the vector processing unit. This paper presents a vector floating- point MAF unit based on AltiVec technology. Pre-normalization logic is added to traditional floating-point structure to deal with denormalized number in java mode. It also proposes a semi parallel structure to construct the vector floating-point MAF unit, and it will have a 50% reduction in area compared with traditional full-parallel structure. It need five clock cycles in java mode, four clock cycles in nonjava mode, under clock rate of 266MHZ.
出处 《计算机测量与控制》 CSCD 北大核心 2010年第1期153-156,共4页 Computer Measurement &Control
基金 国家自然基金(60773223) 国家自然基金重点项目(60736012)
关键词 AltiVec 浮点乘加器 java模式 预规格化 AltiVec floating point multiply-add fused java mode pre-normalization
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参考文献4

  • 1Romesh M. Jessani and Michael Putrino. Comparison of Single and Dual-Pass Multiply-Add Fused Floating-Point Units [J]. IEEE Transactions on Computers, 1998, 47 (9) : 927 - 937.
  • 2Lang T. Bruguera J D. Floating-Point Multiply-Add-Fused with Reduced Latency [J]. IEEE Transac-Tions on Computers, 2004, 53 (8) : 988- 1003.
  • 3Li G Q, Li Z L. Design of a Fully-Pipelined Single Precision Multiply-Add-Fused Unit [A]. 20th International Conferenee on VLSI Design [C]. IEEE Computer Society, 2007.
  • 4ANSI/IEEE Std. 754 - 1985. IEEE Standard for Binary Floating- Point Arithmetic[S]. IEEE Standards Board, 1985.

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