摘要
DSP处理器通过采用VLIW结构获得了高性能,同时也增加了编译器为其生成汇编代码的难度.代码生成器作为编译器的代码生成部件,是VLIW结构能够发挥性能的关键.由此提出并实现了一种基于可重定向编译框架的代码生成器.该代码生成器充分利用VLIW的体系结构特点,支持SIMD指令,支持谓词执行,能够生成高度指令级并行的汇编代码,显著提高应用程序的执行性能.
VLIW architecture is used to enhance the performance of DSP, but also poses a challenge to compiler to generate efficient code for it. As code generation unit of compiler, code generator plays an important role in exploiting VLIW techniques. A code generator based on retargetable compilation infrastructure is proposed and implemented in this paper. It employs the efficient hardware in VLIW structure to greatest extend, supports both SIMD instructions and predication execution, and is able to generate high instruction-level-parallelism assembly code, which greatly improves performance of applications.
出处
《微电子学与计算机》
CSCD
北大核心
2010年第2期9-12,共4页
Microelectronics & Computer
关键词
VLIW
代码生成
指令级并行度
可重定向编译
VLIW
code generation
instruction level parallelism
retargetable compilation
