甚低功耗15Ms/s逐次逼近型ADC的设计实现

Design of Ultra-low Power 15Ms/s SAR ADC

采用一种新颖的甚低功耗SARADC结构技术,基于SMIC0.18μmCMOS工艺,设计实现了一个8bit、15Ms/sSARADC的芯片电路.该ADC利用电荷分享技术实现数据的采样/保持和逐次逼近转换过程,同时采用了异步时序控制技术代替传统的同步时序控制方式,对SAR控制逻辑进行优化设计,使其在功耗和速度方面都达到优良的性能.仿真结果显示该ADC能在15Ms/s的采样率下正常工作,平均功耗仅为518μW,整体性能优值FOM值达到了0.18pJ/Conv,远低于传统结构.

The analog-to-digital converters of low power-consumption are playing more and more important roles in designing SOC and micro-controllers at present. Based on new ultra-low power SAR ADC architecture, an 8bit, 15Msps SAR ADC is implemented in SMIC 0.18μm CMOS process. Instead of traditional active charge redistribution, the method of passive charge sharing is used to both sample the input signal and to perform the binary-scaled feedback during the successive approximation, an asynchronous SAR controller is implemented and optimizes the control logic. The simulation shows that the ADC works very well at the sampling rate of 15Msps, and consumes only 518μW in total. The FOM of the ADC is 0.18pJ/Conv, which is much lower than traditional SAR ADC.