基于AMBA总线的SPI协议IP核的设计与验证

Design and verification of IP core of SPI protocol based on AMBA Bus

基于AMBA总线接口,设计了一个可灵活配置为Master/Slave模式、可设置传输速率并能适用于4种时钟模式的SPI协议IP核。详细说明了该IP核的系统构架、接口信号和子模块设计,使用VerilogHDL实现硬件设计,通过FPGA时序仿真,验证了该设计在实际工程应用中的有效性。

Nowadays the application of SPI Bus is keep growing, and IP core of SPI protocol has become a hot spot in IC design field. However, the functionality of the designs already presented is not ample. Usually they couldn＇t function as SPI Slave, or couldn＇t transmit and receive data in all four clock modes. Based on AMBA Bus, we designed an IP core of SPI protocol, which could be configured as SPI Master or SPI Slave, could set different transmission speed, and could work in any one of the four clock modes. This article introduces the structure, interface and implementation of the IP core using Verilog HDL in detail A simulation example of FPGA timing analysis is presented to show the validity of this design in engineering applications.