摘要
在大规模、超大规模片上互连网络中,因为二维互连方式的性能较差而使多维互连方式成为可选方案之一.文中首先基于区域划分设计了一种分级环互连结构,分析了其静态互连特性,然后基于卡诺图编码设计了一种分级环互连的路由结构以及寻径方法,在均匀通信模式测试了不同的分级环级联链路缓冲区设置方法下网络的性能,详细分析了按照等比序列设置分级环级联链路缓冲区时分级环互连方式的动态网络特性,最后根据互连性能与Mesh等二维片上互连方式比较的结果,给出了分级环互连方式的使用场合.实验结果表明,虽然在较小规模网络中性能较差,但是分级环互连方式能以较低的成本、较高的性能实现大规模、超大规模片上网络的互连,其中单环分级互连方式在较低网络负载下综合性能更好,而双环分级互连方式则具有更大的网络负载能力,在较高网络负载下性能更好.
and ver achieve Networ t The interconnection performance of the 2-D Networks-on-Chip is so poor in the large y large scales that the multi-dimensional interconnections become one of the choices to better interconnection performance This paper gives a design of a kind of hierarchical ring ks-on-Chip based on the regional partition and analyses the static characteristics of the hi- erarchical rings. Then it proposes a kind of the hierarchical ring router and the routing algorithm based on the Karnaugh map coding. It tests the characteristics with different sets of the buffers in the hierarchical router nodes under the uniform random communication pattern and gives a de- tailed analysis of the dynamic characteristics of the hierarchical rings with the buffers in the hier- archical router nodes set in accordance with the geometric sequence under the global uniform ran- dom communication pattern. Finally, it points out the cases when the hierarchical rings work well according to the comparison of the characteristics of the hierarchical ring intereonnections and some of the 2-D Network-on-Chip interconnections such as Mesh. The results show that, al- though working poor in small scales, the hierarchical rings can interconnect the large and very large scales Networks-on-Chip with lower cost and higher performance. Comparatively, the single-hierarchical ring interconnection works better under lower loads and the double-hierarchical ring interconnection has larger load capability and works better under higher loads.
出处
《计算机学报》
EI
CSCD
北大核心
2010年第2期326-334,共9页
Chinese Journal of Computers
基金
国家自然科学基金(60773149)
国家"八六三"高技术研究发展计划项目基金(2006AA01A101
2008AA01Z108)
国家"九七三"重点基础研究发展规划项目基金(2007CB310900)资助
关键词
片上多处理器
片上网络
分级环
性能分析
chip multiprocessor
networks-on-chip
hierarchical ring
performance analysis