基于芯片埋置技术的CiP可靠性分析

Reliability Analysis of CiP Based on Embedded Chip Technology

芯片埋置技术可以提高电子组装密度以及电子产品的可靠性,是微电子封装发展的趋势。建立了聚合物内埋置芯片(CiP)的有限元模型,分析了器件的最大等效应力、剥离应力以及总等效塑性应变,得到该结构容易失效的关键位置。采用修正Coffin-Manson公式对Cu引线的疲劳寿命进行了预测,并分析了Cu引线厚度对其寿命的影响。结果表明,Cu微孔与焊盘交界处的等效应力、剥离应力以及等效塑性应变较大,容易引起裂纹或分层;Cu引线的厚度对疲劳失效起着至关重要的作用,增加Cu引线厚度可以大幅度提高Cu引线的疲劳寿命。

Embedded chip technology can enhance the density of electronic assembly as well as the reliability of electronic products, and it becomes the development trend of microelectronic packaging. The finite element model of embedded chip in polymer （CiP） was built and the maximum equivalent stress, peel stress and equivalent plastic strain were analyzed. The key position of structure failure was obtained. The modified Coffin-Manson formula was employed to predict the fatigue life and the impact of copper line thickness on the fatigue life was surveyed. The results show that the maximum equivalent stress, peel stress and equivalent plastic strain easily lead to crack or delamination, which always appear at the interface of copper vias and pads. The thickness of copper line plays an important role in fatigue failure and increasing the thickness of the copper line will enhance the fatigue life significantly.