摘要
在分析折叠内插ADC预放大电路非线性误差的基础上,设计了一种适用于折叠内插ADC的新型预放大器,有利于减少插值非线性。采用0.35μmCMOS工艺,在3.3V电源电压下进行仿真。结果表明,在0.85V到2.45V输入范围内,预放大器过零点对应的输出电压保持在2.6V,0.1%的容差范围内,建立时间为4.2ns,有利于提高插值精度。
Based on nonlinearity analysis of the preamplifier in folding and interpolation analog-to-digital converters （ADC）, a novel differential difference preamplifier was designed to reduce interpolation nonlinearity. The circuit was simulated based on a 0. 35μm standard CMOS process with single 3. 3 V supply voltage Results showed that the new preamplifier could achieve a steady zero-crossing point output of 2. 6 V in a wide input range from 0. 85 V to 2. 45 V, and it settled in 4. 2 ns to an accuracy of 0. 1%, which is useful for improving interpolation accuracy.
出处
《微电子学》
CAS
CSCD
北大核心
2010年第1期16-19,共4页
Microelectronics
关键词
预放大器
非线性误差
A/D转换器
过零点
Preamplifier
Nonlinearity error
A/D converter
Zero-crossing point
