纳米集成电路的静电放电防护

An Overview of ESD Protection in Nanometer IC

综述了纳米集成电路片上(On-Chip)静电放电防护(ESD)的研究现状;结合自身流片数据,阐述其ESD防护机理和设计要点。从器件ESD防护机理入手,逐步深入分析阐述了纳米集成电路的新特征、纳米器件的失效机制以及基于体硅CMOS工艺和SOI工艺的基本ESD防护器件。在此基础上,对纳米集成电路ESD主要热击穿失效的热量产生机制、热耗散问题,以及边界热电阻对ESD防护带来的影响进行了分析,提出了利用纵向散热路径和工艺整合方案来提高纳米集成电路中ESD防护器件鲁棒性的有效措施。

On-chip ESD protection design for nanometer IC was reviewed, including characteristics of nanometer IC, failure mechanism and cases analyses of nanometer device, basic ESD protection elements based on advanced CMOS bulk and SOI technology. Heat generation and dissipation, and boundary thermal resistance were investigated, as well as their effects on ESD protection for nanometer IC. Two novel concepts of vertical thermal diffusion and process integration were proposed to enhance the robustness of ESD protection in nanometer IC.