摘要
介绍了AES中的S-BOX和INV-S-BOX的算法原理,分析目前广泛使用的实现S-BOX和INV-S-BOX的三种方法:直接查表法,扩展欧几里德算法和基于复合域GF((22)2)2)的算法。对直接查表法和基于复合域GF((22)2)2)的算法进行改进,提出了两种改进电路结构。通过综合仿真,给出了按照上述方法实现的硬件电路的面积和关键路径上的时间延迟。结果表明,提出的两种新实现方法与传统实现方法相比,电路面积分别有28%和22%的优化。
Algorithms for S-BOX and INV-S-BOX modules in AES were described, and three methods to imple ment S-BOX and INV-S-BOX were analyzed, namely, direct kook-up table, extended Euclidean algorithm and composite Galois Field (GF)-based algorithm (2^ 2^ 2^ 2). Based on the improved direct look-up table method and modified composite GF(2^ 4^2)-based algorithm, two circuit structures were proposed. By compilation and simulation, the size and minimum delay of critical routes were obtained for circuits implemented with the proposed methods. Compared with conventional methods, the two novel algorithms could achieve 28% and 22% reduction, respectively, in circuit area.
出处
《微电子学》
CAS
CSCD
北大核心
2010年第1期103-107,共5页
Microelectronics
基金
浙江省高科技基金资助项目(2006C11107)